Meer over Michael D. Ciletti

Michael D. Ciletti

Advanced Digital Design with the Verilog HDL

Name: Advanced Digital Design with the Verilog HDL
Author: Michael D. Ciletti

E-book Engels 2011 9780133002546

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This is the eBook of the printed book and may not include any media, website access codes, or print supplements that may come packaged with the bound book.

Advanced Digital Design with the Verilog HDL, 2e, is ideal for an advanced course in digital design for seniors and first-year graduate students in electrical engineering, computer engineering, and computer science.

This book builds on the student's background from a first course in logic design and focuses on developing, verifying, and synthesizing designs of digital circuits. The Verilog language is introduced in an integrated, but selective manner, only as needed to support design examples (includes appendices for additional language details). It addresses the design of several important circuits used in computer systems, digital signal processing, image processing, and other applications.

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ISBN13:9780133002546

Taal:Engels

Bindwijze:e-book

Uitgever:Pearson Education

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1 Introduction to Digital Design Methodology 1 1.1 Design Methodology–An Introduction 1.1.1 Design Specification 1.1.2 Design Partition 1.1.3 Design Entry 1.1.4 Simulation and Functional Verification 1.1.5 Design Integration and Verification 1.1.6 Presynthesis Sign-Off 1.1.7 Gate-Level Synthesis and Technology Mapping 1.1.8 Postsynthesis Design Validation 1.1.9 Postsynthesis Timing Verification 1.1.10 Test Generation and Fault Simulation 1.1.11 Placement and Routing 1.1.12 Physical and Electrical Design Rule Checks 1.1.13 Parasitic Extraction 1.1.14 Design Sign-Off 1.2 IC Technology Options 1.3 Overview References   2 Review of Combinational Logic Design 13 2.1 Combinational Logic and Boolean Algebra 2.1.1 ASIC Library Cells 2.1.2 Boolean Algebra 2.1.3 DeMorgan’s Laws 2.2 Theorems for Boolean Algebraic Minimization 2.3 Representation of Combinational Logic 2.3.1 Sum-of-Products Representation 2.3.2 Product-of-Sums Representation 2.4 Simplification of Boolean Expressions 2.4.1 Simplification with Exclusive-Or 2.4.2 Karnaugh Maps (SOP Form) 2.4.3 Karnaugh Maps (POS Form) 2.4.4 Karnaugh Maps and Don’t-Cares 2.4.5 Extended Karnaugh Maps 2.5 Glitches and Hazards 2.5.1 Elimination of Static Hazards (SOP Form) 2.5.2 Summary: Elimination of Static Hazards in Two-Level Circuits 2.5.3 Static Hazards in Multilevel Circuits 2.5.4 Summary: Elimination of Static Hazards in Multilevel Circuits 2.5.5 Dynamic Hazards 2.6 Building Blocks for Logic Design 2.6.1 NAND—NOR Structures 2.6.2 Multiplexers 2.6.3 Demultiplexers 2.6.4 Encoders 2.6.5 Priority Encoder 2.6.6 Decoder 2.6.7 Priority Decoder References Problems   3 Fundamentals of Sequential Logic Design 69 3.1 Storage Elements 3.1.1 Latches 3.1.2 Transparent Latches 3.2 Flip-Flops 3.2.1 D-Type Flip-Flop 3.2.2 Master—Slave Flip-Flop 3.2.3 J-K Flip-Flops 3.2.4 T Flip-Flop 3.3 Busses and Three-State Devices 3.4 Design of Sequential Machines 3.5 State-Transition Graphs 3.6 Design Example: BCD to Excess-3 Code Converter 3.7 Serial-Line Code Converter for Data Transmission 3.7.1 Design Example: A Mealy-Type FSM for Serial Line-Code Conversion 3.7.2 Design Example: A Moore-Type FSM for Serial Line-Code Conversion 3.8 State Reduction and Equivalent States References Problems   4 Introduction to Logic Design with Verilog 103 4.1 Structural Models of Combinational Logic 4.1.1 Verilog Primitives and Design Encapsulation 4.1.2 Verilog Structural Models 4.1.3 Module Ports 4.1.4 Some Language Rules 4.1.5 Top-Down Design and Nested Modules 4.1.6 Design Hierarchy and Source-Code Organization 4.1.7 Vectors in Verilog 4.1.8 Structural Connectivity 4.2 Logic System, Design Verification, and Test Methodology 4.2.1 Four-Value Logic and Signal Resolution in Verilog 4.2.2 Test Methodology 4.2.3 Signal Generators for Testbenches 4.2.4 Event-Driven Simulation 4.2.5 Testbench Template 4.2.6 Sized Numbers 4.3 Propagation Delay 4.3.1 Inertial Delay 4.3.2 Transport Delay 4.4 Truth Table Models of Combinational and Sequential Logic with Verilog References Problems   5 Logic Design with Behavioral Models of Combinational and Sequential Logic 141 5.1 Behavioral Modeling 5.2 A Brief Look at Data Types for Behavioral Modeling 5.3 Boolean Equation-Based Behavioral Models of Combinational Logic 5.4 Propagation Delay and Continuous Assignments 5.5 Latches and Level-Sensitive Circuits in Verilog 5.6 Cyclic Behavioral Models of Flip-Flops and Latches 5.7 Cyclic Behavior and Edge Detection 5.8 A Comparison of Styles for Behavioral Modeling 5.8.1 Continuous Assignment Models 5.8.2 Dataflow/RTL Models 5.8.3 Algorithm-Based Models 5.8.4 Naming Conventions: A Matter of Style 5.8.5 Simulation with Behavioral Models 5.9 Behavioral Models of Multiplexers, Encoders, and Decoders 5.10 Dataflow Models of a Linear-Feedback Shift Register 5.11 Modeling Digital Machines with Repetitive Algorithms 5.11.1 Intellectual Property Reuse and Parameterized Models 5.11.2 Clock Generators 5.12 Machines with Multicycle Operations 5.13 Design Documentation with Functions and Tasks: Legacy or Lunacy? 5.13.1 Tasks 5.13.2 Functions 5.14 Algorithmic State Machine Charts for Behavioral Modeling 5.15 ASMD Charts 5.16 Behavioral Models of Counters, Shift Registers, and Register Files 5.16.1 Counters 5.16.2 Shift Registers 5.16.3 Register Files and Arrays of Registers (Memories) 5.17 Switch Debounce, Metastability, and Synchronizers for Asynchronous Signals 5.18 Design Example: Keypad Scanner and Encoder References Problems   6 Synthesis of Combinational and Sequential Logic 235 6.1 Introduction to Synthesis 6.1.1 Logic Synthesis 6.1.2 RTL Synthesis 6.1.3 High-Level Synthesis 6.2 Synthesis of Combinational Logic 6.2.1 Synthesis of Priority Structures 6.2.2 Exploiting Logical Don’t-Care Conditions 6.2.3 ASIC Cells and Resource Sharing 6.3 Synthesis of Sequential Logic with Latches 6.3.1 Accidental Synthesis of Latches 6.3.2 Intentional Synthesis of Latches 6.4 Synthesis of Three-State Devices and Bus Interfaces 6.5 Synthesis of Sequential Logic with Flip-Flops 6.6 Synthesis of Explicit State Machines 6.6.1 Synthesis of a BCD-to-Excess-3 Code Converter 6.6.2 Design Example: Synthesis of a Mealy-Type NRZ-to-Manchester Line Code Converter 6.6.3 Design Example: Synthesis of a Moore-Type NRZ-to-Manchester Line Code Converter 6.6.4 Design Example: Synthesis of a Sequence Recognizer 284 6.7 Registered Logic 6.8 State Encoding 6.9 Synthesis of Implicit State Machines, Registers, and Counters 6.9.1 Implicit State Machines 6.9.2 Synthesis of Counters 6.9.3 Synthesis of Registers 6.10 Resets 6.11 Synthesis of Gated Clocks and Clock Enables 6.12 Anticipating the Results of Synthesis 6.12.1 Synthesis of Data Types 6.12.2 Operator Grouping 6.12.3 Expression Substitution 6.13 Synthesis of Loops 6.13.1 Static Loops without Embedded Timing Controls 6.13.2 Static Loops with Embedded Timing Controls 6.13.3 Nonstatic Loops without Embedded Timing Controls 6.13.4 Nonstatic Loops with Embedded Timing Controls 6.13.5 State-Machine Replacements for Unsynthesizable Loops 6.14 Design Traps to Avoid 6.15 Divide and Conquer: Partitioning a Design References Problems   7 Design and Synthesis of Datapath Controllers 345 7.1 Partitioned Sequential Machines 7.2 Design Example: Binary Counter 7.3 Design and Synthesis of a RISC Stored-Program Machine 7.3.1 RISC SPM: Processor 7.3.2 RISC SPM:ALU 7.3.3 RISC SPM: Controller 7.3.4 RISC SPM: Instruction Set 7.3.5 RISC SPM: Controller Design 7.3.6 RISC SPM: Program Execution 7.4 Design Example: UART 7.4.1 UART Operation 7.4.2 UART Transmitter 7.4.3 UART Receiver References Problems   8 Programmable Logic and Storage Devices 415 8.1 Programmable Logic Devices 8.2 Storage Devices 8.2.1 Read-Only Memory (ROM) 8.2.2 Programmable ROM (PROM) 8.2.3 Erasable ROMs 8.2.4 ROM-Based Implementation of Combinational Logic 8.2.5 Verilog System Tasks for ROMs 8.2.6 Comparison of ROMs 8.2.7 ROM-Based State Machines 8.2.8 Flash Memory 8.2.9 Static Random Access Memory (SRAM) 8.2.10 Ferroelectric Nonvolatile Memory 8.3 Programmable Logic Array (PLA) 8.3.1 PLA Minimization 8.3.2 PLA Modeling 8.4 Programmable Array Logic (PAL) 8.5 Programmability of PLDs 8.6 Complex PLDs (CPLDs) 8.7 Field-Programmable Gate Arrays 8.7.1 The Role of FPGAs in the ASIC Market 8.7.2 FPGA Technologies 8.7.3 XILINX Virtex FPGAs 8.8 Embeddable and Programmable IP Cores for a System-on-a-Chip (SoC) 8.9 Verilog-Based Design Flows for FPGAs 8.10 Synthesis with FPGAs References Related Web Sites Problems and FPGA-Based Design Exercises   9 Algorithms and Architectures for Digital Processors 515 9.1 Algorithms, Nested-Loop Programs, and Data Flow Graphs 9.2 Design Example: Halftone Pixel Image Converter 9.2.1 Baseline Design for a Halftone Pixel Image Converter 9.2.2 NLP-Based Architectures for the Halftone Pixel Image Converter 9.2.3 Minimum Concurrent Processor Architecture for a Halftone Pixel Image Converter 9.2.4 Halftone Pixel Image Converter: Design Tradeoffs 9.2.5 Architectures for Dataflow Graphs with Feedback 9.3 Digital Filters and Signal Processors 9.3.1 Finite-Duration Impulse Response Filter 9.3.2 Digital Filter Design Process 9.3.3 Infinite-Duration Impulse Response Filter 9.4 Building Blocks for Signal Processors 9.4.1 Integrators (Accumulators) 9.4.2 Differentiators 9.4.3 Decimation and Interpolation Filters 9.5 Pipelined Architectures 9.5.1 Design Example: Pipelined Adder 9.5.2 Design Example: Pipelined FIR Filter 9.6 Circular Buffers 9.7 Asynchronous FIFOs–Synchronization across Clock Domains 9.7.1 Simplified Asynchronous FIFO 9.7.2 Clock Domain Synchronization for an Asynchronous FIFO References Problems   10 Architectures for Arithmetic Processors 627 10.1 Number Representation 10.1.1 Signed Magnitude Representation of Negative Integers 10.1.2 Ones Complement Representation of Negative Integers 10.1.3 Twos Complement Representation of Positive and Negative Integers 10.1.4 Representation of Fractions 10.2 Functional Units for Addition and Subtraction 10.2.1 Ripple-Carry Adder 10.2.2 Carry Look-Ahead Adder 10.2.3 Overflow and Underflow 10.3 Functional Units for Multiplication 10.3.1 Combinational (Parallel) Binary Multiplier 10.3.2 Sequential Binary Multiplier 10.3.3 Sequential Multiplier Design: Hierarchical Decomposition 10.3.4 STG-Based Controller Design 10.3.5 Efficient STG-Based Sequential Binary Multiplier 10.3.6 ASMD-Based Sequential Binary Multiplier 10.3.7 Efficient ASMD-Based Sequential Binary Multiplier 10.3.8 Summary of ASMD-Based Datapath and Controller Design 10.3.9 Reduced-Register Sequential Multiplier 10.3.10 Implicit-State-Machine Binary Multiplier 10.3.11 Booth’s Algorithm Sequential Multiplier 10.3.12 Bit-Pair Encoding 10.4 Multiplication of Signed Binary Numbers 10.4.1 Product of Signed Numbers: Negative Multiplicand, Positive Multiplier 10.4.2 Product of Signed Numbers: Positive Multiplicand, Negative Multiplier 10.4.3 Product of Signed Numbers: Negative Multiplicand, Negative Multiplier 10.5 Multiplication of Fractions 10.5.1 Signed Fractions: Positive Multiplicand, Positive Multiplier 10.5.2 Signed Fractions: Negative Multiplicand, Positive Multiplier 10.5.3 Signed Fractions: Positive Multiplicand, Negative Multiplier 10.5.4 Signed Fractions: Negative Multiplicand, Negative Multiplier 10.6 Functional Units for Division 10.6.1 Division of Unsigned Binary Numbers 10.6.2 Efficient Division of Unsigned Binary Numbers 10.6.3 Reduced-Register Sequential Divider 10.6.4 Division of Signed (2s Complement) Binary Numbers 10.6.5 Signed Arithmetic References Problems   11 Postsynthesis Design Tasks 749 11.1 Postsynthesis Design Validation 11.2 Postsynthesis Timing Verification 11.2.1 Static Timing Analysis 11.2.2 Timing Specifications 11.2.3 Factors That Affect Timing 11.3 Elimination of ASIC Timing Violations 11.4 False Paths 11.5 System Tasks for Timing Verification 11.5.1 Timing Check: Setup Condition 11.5.2 Timing Check: Hold Condition 11.5.3 Timing Check: Setup and Hold Conditions 11.5.4 Timing Check: Pulsewidth Constraint 11.5.5 Timing Check: Signal Skew Constraint 11.5.6 Timing Check: Clock Period 11.5.7 Timing Check: Recovery Time 11.6 Fault Simulation and Manufacturing Tests 11.6.1 Circuit Defects and Faults 11.6.2 Fault Detection and Testing 11.6.3 D-Notation 11.6.4 Automatic Test Pattern Generation for Combinational Circuits 11.6.5 Fault Coverage and Defect Levels 11.6.6 Test Generation for Sequential Circuits 11.7 Fault Simulation 11.7.1 Fault Collapsing 11.7.2 Serial Fault Simulation 11.7.3 Parallel Fault Simulation 11.7.4 Concurrent Fault Simulation 11.7.5 Probabilistic Fault Simulation 11.8 JTAG Ports and Design for Testability 11.8.1 Boundary Scan and JTAG Ports 11.8.2 JTAG Modes of Operation 11.8.3 JTAG Registers 11.8.4 JTAG Instructions 11.8.5 TAP Architecture 11.8.6 TAP Controller State Machine 11.8.7 Design Example:Testing with JTAG 11.8.8 Design Example: Built-In Self-Test References Problems   A Verilog Primitives 851 A.1 Multiinput Combinational Logic Gates A.2 Multioutput Combinational Gates A.3 Three-State Logic Gates A.4 MOS Transistor Switches A.5 MOS Pull-Up/Pull-Down Gates A.6 MOS Bidirectional Switches   B Verilog Keywords 863 C Verilog Data Types 865 C.1 Nets C.2 Register Variables C.3 Constants C.4 Referencing Arrays of Nets or Regs   D Verilog Operators 873 D.1 Arithmetic Operators D.2 Bitwise Operators D.3 Reduction Operators D.4 Logical Operators D.5 Relational Operators D.6 Shift Operators D.7 Conditional Operator D.8 Concatenation Operator D.9 Expressions and Operands D.10 Operator Precedence D.11 Arithmetic with Signed Data Types D.12 Signed Literal Integers D.13 System Functions for Sign Conversion 2.1.1 Assignment Width Extension   E Verilog Language Formal Syntax 885 F Verilog Language Formal Syntax 887 F.1 Source text F.2 Declarations F.3 Primitive instances F.4 Module and generated instantiation F.5 UDP declaration and instantiation F.6 Behavioral statements F.7 Specify section F.8 Expressions F.9 General   G Additional Features of Verilog 913 G.1 Arrays of Primitives G.2 Arrays of Modules G.3 Hierarchical Dereferencing G.4 Parameter Substitution G.5 Procedural Continuous Assignment G.6 Intra-Assignment Delay G.7 Indeterminate Assignment and Race Conditions G.8 wait STATEMENT G.9 fork join Statement G.10 Named (Abstract) Events G.11 Constructs Supported by Synthesis Tools   H Flip-Flop and Latch Types 925 I Verilog-2001, 2005 927 I.1 ANSI C Style Changes I.2 Code Management I.3 Support for Logic Modeling I.4 Support for Arithmetic I.5 Sensitivity List for Event Control I.6 Sensitivity List for Combinational Logic I.7 Parameters I.8 Instance Generation J Programming Language Interface 949 K Web sites 951 L Web-Based Resources 953 Index 965

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