High Speed CMOS Design Styles

1 Process Variability.- 1.1 Introduction.- 1.2 Front-End-Of-Line Variability Considerations.- 1.3 Charge Loss Mechanisms.- 1.4 Back-End-Of-Line Variability Considerations.- 1.5 Summary.- 2 Non-Clocked Logic Styles.- 2.1 Introduction.- 2.2 Static CMOS Structures.- 2.3 DCVS Logic.- 2.4 Non-Clocked Pass-Gate Families.- 2.5 Summary.- 3 Clocked Logic Styles.- 3.1 Introduction.- 3.2 Single-Rail Domino Logic Styles.- 3.3 Alternating-Polarity Domino Approaches.- 3.4 Dual-Rail Domino Structures.- 3.5 Latched Domino Structures.- 3.6 Clocked Pass-Gate Logic.- 3.7 Summary.- 4 Circuit Design Margin and Design Variability.- 4.1 Introduction.- 4.2 Process Induced Variation.- 4.3 Design Induced Variation.- 4.4 Application Induced Variation.- 4.5 Noise.- 4.6 Design Margin Budgeting.- 4.7 Summary.- 5 Latching Strategies.- 5.1 Introduction.- 5.2 Basic Latch Design.- 5.3 Latching Single-Ended Logic.- 5.4 Latching Differential Logic.- 5.5 Race Free Latches for Precharged Logic.- 5.6 Asynchronous Latch Techniques.- 5.7 Summary.- 6 Interface Techniques.- 6.1 Introduction.- 6.2 Signaling Standards.- 6.3 Chip-to-chip Communication Networks.- 6.4 ESD Protection.- 6.5 Driver Design Techniques.- 6.6 Receiver Design Techniques.- 6.7 Summary.- 7 Clocking Styles.- 7.1 Introduction.- 7.2 Clock Jitter and Skew.- 7.3 Clock Generation.- 7.4 Clock Distribution.- 7.5 Single Phase Clocking.- 7.6 Multi-Phase Clocking.- 7.7 Asynchronous Techniques.- 7.8 Summary.- 8 Slack Borrowing and Time Stealing.- 8.1 Introduction.- 8.2 Slack Borrowing.- 8.3 Time Stealing.- 8.4 Summary.- 9 Future Technology.- 9.1 Introduction.- 9.2 Classical Scaling Theory.- 9.3 Industry Trends Define Scaling Law.- 9.4 Challenges Presented by I/S Scaling.- 9.5 Possible Directions.