VLSI Systems and Computations

Invited Papers.- The Optical Mouse, and an Architectural Methodology for Smart Digital Sensors.- Designing a VLSI Processor — Aids and Architectures.- Keys to Successful VLSI System Design.- Programmable LSI Digital Signal Processor Development.- Functional Parallelism in VLSI Systems and Computations.- Functional Extensibility: Making The World Safe for VLSI.- Models of Computation.- Replication of Inputs May Save Computational Resources in VLSI.- Planar Circuit Complexity and the Performance of VLSI Algorithms.- Three-Dimensional Integrated Circuitry.- A Critique and an Appraisal of VLSI Models of Computation.- Complexity Theory.- On the Complexity of VLSI Computations.- On the Area Required by VLSI Circuits.- The VLSI Complexity of Sorting.- Minimum Edge Length Planar Embeddings of Trees.- The VLSI Approach to Computational Complexity.- Layout Theory and Algorithms.- Optimal Placement for River Routing.- The Separation for General Single-Layer Wiring Barriers.- Provably Good Channel Routing Algorithms.- Optimal Routing in Rectilinear Channels.- New Lower Bounds for Channel Width.- Compact Layouts of Banyan/FFT Networks.- Languages and Verification.- Syntax-Directed Verification of Circuit Function.- Temporal Specifications of Self-Timed Systems.- A Mathematical Approach to Modelling the Flow of Data and Control in Computational Networks.- A Wavefront Notation Tool for VLSI Array Design.- A Matrix Data Flow Language/Architecture for Parallel Matrix Operations Based on Computational Wavefront Concept.- Special-Purpose Architectures.- Digital Signal Processing Applications of Systolic Algorithms.- A Two-Level Pipelined Systolic Array for Convolutions.- Systolic Algorithms for Running Order Statistics in Signal and Image Processing.- Systolic Array Processor Developments.- A Systolic (VLSI) Array for Processing Simple Relational Queries.- A Systolic Data Structure Chip for Connectivity Problems.- Multiplier Designs.- Fixed-Point High-Speed Parallel Multipliers in VLSI.- A Mesh-Connected Area-Time Optimal VLSI Integer Multiplier.- A Regular Layout for Parallel Multiplier of O(log2n) Time.- Processors.- VLSI Implementations of a Reduced Instruction Set Computer.- MIPS: A VLSI Processor Architecture.- Comparative Survey of Different Design Methodologies for Control Parts of Microprocessors.- C.FAST: A Fault Tolerant and Self Testing Microprocessor.- Systems and Processors.- VLSI Processor Arrays for Matrix Manipulation.- A General-Purpose CAM-Based System.- A Statically Scheduled VLSI Interconnect for Parallel Processors.- The CMOS SLA Implementation and SLA Program Structures.- A New CCD Parallel Processing Architecture.