VLSI AND PARALLEL COMPUTING FOR PATTERN RECOGNITION AND ARTIFICIAL INTELLIGENCE

ENPASSANT - an environment for evaluating massively parallel array architectures for spatially mapped applications, M.C. Herbordt and C.C. Weems; a reconfigurable architecture for image processing and computer vision, S.M. Bhandarkar et al; a design methodology for very large array processors - part 1 - GIPOP processor array, N. Venkateswaran et al; a design methodology for very large array processors - part II - PACUBE VLSI arrays, N. Venkateswaran et al; a VLSI implementation of inverse discrete cosine transform, A.K. Bhattacharya and S.S. Haider; systolic merging and ranking of votes for the generalized hough transform, M. Albanesi and M. Ferretti; high speed parallel VLSI architectures for image decorrelation, T. Acharya and A. Mukherjee; PMAC - a polygon matching chip, R. Sastry and N. Ranganathan; quadtree algorithms for template matching on mesh connected computer, H. Senoussi and A. Saoudi; fast pattern-matching algorithm on modular mesh-connected computers with multiple buses, K.L. Chung; a VLSI parallel architecture for fuzzy expert systems, V. Catania and G. Ascia; efficient architecture for image rotation and its implementation in real time, B. Majumdar and I. Ghosh.